行业组件数据 · 2026

晶圆衬底

晶圆衬底是半导体材料(通常为硅)制成的薄圆片,具有极高的尺寸精度和表面特性,是微电子器件制造的基础。

技术定义与适配语境
典型 晶圆衬底 会按材料、尺寸公差、适配关系和失效风险在 计算机、电子和光学产品制造 中评估。

晶圆衬底是半导体材料(通常为硅)制成的薄圆片,具有极高的尺寸精度和表面特性。它作为物理基础,通过光刻、掺杂、沉积和蚀刻工艺在其上构建微电子器件。衬底为集成电路提供机械支撑、热管理和电气隔离。现代衬底直径从100mm到450mm,厚度从275μm到925μm,表面超平坦,粗糙度低于0.1nm RMS。 晶圆衬底既作为结构平台,又作为有源半导体材料。在制造过程中,衬底材料(通常为单晶硅)的晶体结构为外延生长和器件形成提供晶格框架。衬底的电气特性(电阻率、载流子浓度)决定器件性能。热导率有助于运行时的散热,而机械刚性则支撑多层器件结构经过数百道工艺步骤。

组件规格

定义
晶圆衬底是半导体材料(通常为硅)制成的薄圆片,具有极高的尺寸精度和表面特性。它作为物理基础,通过光刻、掺杂、沉积和蚀刻工艺在其上构建微电子器件。衬底为集成电路提供机械支撑、热管理和电气隔离。现代衬底直径从100mm到450mm,厚度从275μm到925μm,表面超平坦,粗糙度低于0.1nm RMS。

晶圆衬底既作为结构平台,又作为有源半导体材料。在制造过程中,衬底材料(通常为单晶硅)的晶体结构为外延生长和器件形成提供晶格框架。衬底的电气特性(电阻率、载流子浓度)决定器件性能。热导率有助于运行时的散热,而机械刚性则支撑多层器件结构经过数百道工艺步骤。
工作原理
The wafer substrate functions as both a structural platform and active semiconductor material. During fabrication, the crystalline structure of the substrate material (typically monocrystalline silicon) provides the lattice framework for epitaxial growth and device formation. The substrate's electrical properties (resistivity, carrier concentration) determine device performance characteristics. Thermal conductivity enables heat dissipation during operation, while mechanical rigidity supports the multilayer device structure through hundreds of processing steps.
材料
主要材料:单晶硅(CZ或FZ法生长)直径:100-450mm厚度:275-925μm晶向:<100>、<110>或<111>电阻率:0.001-1000 Ω·cm掺杂剂:硼(p型)、磷/砷(n型)氧含量:<10 ppma碳含量:<0.1 ppma表面粗糙度:<0.1nm RMS翘曲度/弯曲度:<50μm。次要材料:碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)、蓝宝石(Al₂O₃)、锗(Ge)。
Diameter
100mm, 150mm, 200mm, 300mm, 450mm
Thickness
275μm, 525μm, 625μm, 775μm, 925μm
Resistivity
0.001-1000 Ω·cm
Local Flatness
<0.2μm
Particle Count
<10 particles >0.2μm per wafer
Global Flatness
<10μm
Surface Roughness
<0.1nm RMS
Primary Flat Length
Varies by diameter
Surface Orientation
<100>, <110>, <111>
Carbon Concentration
<0.1 ppma
Oxygen Concentration
5-18 ppma
Secondary Flat Length
Varies by diameter
Total Thickness Variation
<2μm
标准
ISO 14644-1SEMI M1SEMI M20SEMI M43SEMI M59ASTM F1241ASTM F1530JIS H 0601

行业分类与别名

晶圆衬底 的常用贸易名称、技术标识和检索关键词。

上级产品

该组件会出现在以下整机或工业产品中。

FMEA · 风险与缓解

诱因 → 失效模式 → 工程缓解

Improper crystal growth conditions->Crystalline defects (dislocations, vacancies)->Precise control of temperature gradients, pull rates, and rotation during Czochralski growth; regular quality testing using X-ray topography
Contamination during handling or storage->Surface particles or organic residues affecting lithography->Cleanroom protocols (ISO Class 1-3), automated handling systems, proper wafer carrier design, regular particle monitoring
Thermal stress during processing->Wafer warpage or bow exceeding specifications->Controlled ramp rates during thermal processes, optimized wafer support designs, stress measurement after each high-temperature step

工业生态与工程逻辑

0
Crystal defects (dislocations, stacking faults)
1
Surface contamination (particles, organic residues)
2
Wafer warpage/bowing
3
Dopant concentration variations
4
Oxygen precipitation issues
5
Mechanical damage (chips, cracks)
6
Metallic contamination
7
Electrical property non-uniformity

合规与检测

tolerance
Diameter: ±0.2mm, Thickness: ±15μm, Bow: <50μm, Warp: <50μm, TTV: <2μm, Surface roughness: <0.1nm RMS, Resistivity: ±10% of target
test method
Diameter: Laser scanning, Thickness: Capacitance gauge, Bow/Warp: Non-contact optical measurement, Surface roughness: Atomic force microscopy, Resistivity: Four-point probe, Crystal quality: X-ray diffraction, Contamination: Total reflection X-ray fluorescence

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来自 CNFX 组件能力表的相关制造商资料。

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采购评估维度

不是客户评论,也不是实时热度。以下维度用于前期 RFQ 准备和供应商评估。

技术文档
4/5
制造能力
4/5
可检验性
5/5
供应商透明度
3/5

这些分值是采购评估维度示例,不代表真实客户评分、具体国家买家反馈或实时询盘。

相关组件

常见问题

What is the difference between a wafer substrate and a wafer?

The terms are often used interchangeably, but technically the wafer substrate refers specifically to the base semiconductor material before any device fabrication, while 'wafer' can refer to the substrate at any stage of processing, including after device layers have been added.

Why are most wafer substrates made from silicon?

Silicon is abundant, forms a stable oxide (SiO₂) that serves as an excellent insulator, has suitable electrical properties that can be precisely controlled through doping, and can be grown into large, high-quality monocrystalline ingots with minimal defects.

What determines the choice of wafer substrate diameter?

Diameter selection balances manufacturing efficiency (more chips per wafer) with technical challenges (larger wafers are harder to produce with uniform properties and require more expensive equipment). The industry has progressed from 100mm to 300mm as the standard, with 450mm in development.

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